IEEE Spectrum (Jan. 31) -- At the Institute of Electrical and Electronics Engineers International Symposium on High-Performance Computer Architecture in February, Rakesh Kumar, a professor of computer engineering at Illinois, and his collaborators will make the case for a wafer-scale computer consisting of as many as 40 graphics-processing units. Simulations of this multiprocessor monster sped calculations nearly 19-fold and cut the combination of energy consumption and signal delay more than 140-fold.