NSF funds research to advance scalability for on-chip wireless communications

Researchers in the Department of Computer Science have received a grant from the National Science Foundation for their proposal "XPS: FULL: Breaking the Scalability Wall of Shared Memory through Fast On-Chip Wireless Communication." Funding for the project—under the direction of computer science professors Josep Torrellas and David A. Padua, and assistant professor Sasa Misailovic—is expected to total nearly $880,000.

“As transistor sizes continue to scale, we are about to witness stunning levels of chip integration, with 1,000 cores on a single die,” explained Josep Torrellas, the Saburo Muroga Professor of Computer Science at Illinois who will serve as principal investigator (PI) for the project. “At these processor counts, it has been an accepted tenet among many researchers that shared memory does not scale. The reason is the high hardware overhead of supporting fine-grain synchronization and communication between so many cores.

“Our proposal seeks to disprove this. It shows that fine-grain data sharing is scalable with the use of fast on-chip wireless communication. We augment each core with a transceiver that enables on-chip broadcast in 5-7 ns, and design a multicore architecture that supports it. We then implement synchronization and communication primitives and libraries that support fine-grain data sharing with an unprecedented low overhead. With these primitives, we redesign popular runtimes such as OpenMP or Cilk, and rethink algorithms and applications.

“This is a cross-disciplinary effort that cuts across three areas: architecture, programming systems, and algorithms and applications,” added Padua, who is the Donald Biggar Willett Professor in computer science at Illinois. “The architecture work focuses on supporting on-chip wireless communication by extending cache coherence transactions, trading-off wireless power for error rate, and supporting multiple wireless channels.

“The programming systems work focuses on redesigning the MPI communication primitives, making shared memory scalable for OpenMP and Cilk, and designing a best-effort API for application resiliency. The algorithms and applications work focuses on studying and developing algorithms and applications that can take advantage of the architecture. We study problems in the areas of graphs, numerics, dynamic programming, recognition-mining-synthesis, and MapReduce.”

Earlier research supporting the project was published in the paper, “WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication” (Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcon, and Josep Torrellas) in the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) in April 2016.

The project’s research team includes two Illinois’ alumni representing key industry partners—Dr. Jose Moreira from IBM Research (PhD, 1995, Electrical Engineering; technical lead for POWER© Servers) and Dr. Saeed Maleki from Microsoft Research (PhD 2015, Computer Science; expert in efficient parallel algorithms).

“This effort will contribute to multidisciplinary research and education on scalable parallel computing here at Illinois,” Torrellas said. “We feel that the work will also have a major impact on industry, since it addresses a real, very timely technical problem: extraordinary on-chip integration coupled with un-scalable fine-grain data sharing. The ability to work closely with IBM Research and Microsoft Research is crucial, and the IT community at large will benefit, as this is fundamental research that will enable scalable fine-grain data sharing.”
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