Error-free hardware? GoldMine guarantees it

Shobha Vasudevan, a researcher at the Coordinated Science Laboratory, has developed a tool that makes it easier to detect hardware errors during the verification stage of the semiconductor design cycle.

GoldMine is an automatic assertion generation tool that integrates formal verification and data mining to guarantee reliable, fault-free hardware. The methodology was presented at the DATE 2010 and 2011 conferences and, more recently, at this spring’s DVCon 2011 conference, where EDA journalists selected it as one of the most interesting tools.

“When you don’t have enough coverage in your design validation, you could be making hardware that has flaws in it,” said Vasudevan, an assistant professor of electrical and computer engineering. “It could cost millions of dollars if you’re a semiconductor company and have to recall your hardware. If you’re an airline or car company and your hardware fails, it could cost lives.”

GoldMine is a one-of-a-kind tool that uses both formal verification and data mining to generate assertions. Formal verification provides content for the design that helps guide the data mining, which infers patterns from simulation data. It proffers a solution to the troublesome coverage closure problem faced by designers and verification engineers, who often don’t know how many tests to run to ensure that a design is bug-free. It can be used for formal verification, simulation-based verification or even post-silicon verification.

“When the formal verification says that something is false, it gives us a reason why it’s false,” said Vasudevan, who received a CAREER Award for GoldMine in 2010. “We plug these counterexamples back into GoldMine, which adjusts for the new information. As we do this iteratively, we reach a point where there’s no more counterexamples and we have reached a complete test set.”

Vasudevan and her student David Sheridan initially developed GoldMine in 2009, when they used the Rigel multicore architecture developed by CSL researcher Sanjay Patel as a test bed for the tool. Subsequently, Vasudevan’s team, which consists of four graduate students, managed to scale GoldMine to the open source UltraSparc processor.

Several companies are already using the technology, for which the University is currently seeking licensing. In addition to verification, GoldMine could be used for other phases of the design cycle, such as reliability and fault detection. That would open up applications in security, including monitoring and detecting hardware trojans.

For Vasudevan’s team, the next step is to apply GoldMine’s techniques to software. Vasudevan believes that by using data mining to create likely assertions in software systems, GoldMine can give developers a high level of confidence in their products.

“The idea of using data mining with formal tools is something that hasn’t been explored before,” she said. “As a result, the net effect is very powerful, evidenced by the interest the tool has received from companies.”
____________________

Contact: Shobha Vasudevan, Department of Electrical and Computer Engineering, 217/333-8164.

Writer: Kim Gudeman, Coordinated Science Laboratory.

If you have any questions about the College of Engineering, or other story ideas, contact Rick Kubetz, editor, Engineering Communications Office, University of Illinois at Urbana-Champaign, 217/244-7716.