Researchers from the University of Illinois won the Best Paper Award at the International Symposium on Microarchitecture (MICRO) for their work entitled "The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration." MICRO is the premier forum for presenting, discussing and debating new and innovative microarchitecture ideas and techniques for advanced computing and communication systems.
The research team, including computer science professor Josep Torrellas, computer science alumnus Brian Greskamp, and electrical and computer engineering student Ulya R. Karpuzcu discuss promising new methods for pushing back the power wall for multicore computing architectures.
"Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly increasing with technology scaling," said Torrellas. "In future designs, many of the cores may have to be dormant at any given time to meet the power budget."
For many-core architectures, designed to increase system performance to meet today’s computing needs, having processors lie dormant because of power restrictions can be a self-defeating proposition.
In their paper, the team proposes to push back the many-core power wall with a new scheme called Dynamic Voltage Scaling for Aging Management (DVSAM). The team’s system manages processor aging to attain higher performance or lower power consumption.
To make use of this new scheme, the team developed BubbleWrap, a novel many-core architecture that identifies the most power-efficient set of cores in a variation-affected chip—the largest set that can be simultaneously powered-on. BubbleWrap then designates those cores as Throughput cores dedicated to parallel-section execution. The rest of the cores are designated as Expendable and are dedicated to accelerating sequential sections. BubbleWrap attains maximum sequential acceleration by sacrificing Expendable cores one at a time, running them at elevated supply voltage for a significantly shorter service life each, until they completely wear-out and are discarded.
The team was also able to demonstrate significant performance increases. In simulated 32-core chips, BubbleWrap provides substantial gains over a plain chip with the same power envelope. On average, the most aggressive design runs fully-sequential applications at a 16% higher frequency, and fully-parallel ones with a 30% higher throughput.
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Contact: Josep Torrellas, Department of Computer Science, 217/244-4148.
Jennifer LaMontagne, associate director of communications, Department of Computer Science, 217/333-4049.
If you have any questions about the College of Engineering, or other story ideas, contact Rick Kubetz, Engineering Communications Office, 217/244-7716, editor.